1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
As a semiconductor device used as a power semiconductor device, an insulated gate bipolar transistor (IGBT) having a breakdown voltage of 400V, 600V, 1200V, 1700V, 3300V, or more, or the like, is publically known. The IGBT is used in a power conversion device such as a converter or an inverter. This kind of power semiconductor device is required to have a low loss, a high efficiency, and a high withstand capacity, and measures for having a low noise, that is, electro-magnetic compatibility (EMC) are required of the power semiconductor device.
The EMC depends on the time rate of change in voltage (dV/dt), and the dV/dt of free wheeling diodes (FWDs) of opposing arms in a low current region when the IGBT is turned on (when FWDs of opposing arms are reversely recovered) is apt to be highest when the inverter is in operation. Therefore, it is necessary to reduce the dV/dt to an appropriate value by increasing a gate resistance Rg of the IGBT and slowing a turn-on speed, but in this case, turn-on loss Eon of the IGBT increases. Consequently, it is important to improve the trade-off relationship between the turn-on loss Eon and the dV/dt, and improve dV/dt controllability using the gate resistance Rg when the IGBT is turned on (hereafter referred to as turn-on dV/dt controllability).
Next, a description will be given, with a commonly used trench gate IGBT as an example, of a structure of an active region in charge of a current drive of the IGBT. The active region is a region through which a current flows when in an on-state. FIG. 24 is a sectional view showing a structure of a heretofore known trench gage IGBT. As shown in FIG. 24, in the active region, a trench gate type of MOS gate (an insulating gate formed of a metal oxide film semiconductor) structure is provided on the front surface side of an n−-type semiconductor substrate forming an n−-type drift layer 101. Specifically, a trench (hereafter referred to as a gate trench) 102 is provided on the front surface side of the n−-type semiconductor substrate so as to divide the front surface layer of the n−-type drift layer 101. A gate electrode 104 is provided in the inner portion of the gate trench 102 via a gate insulating film 103.
A p-type base region 105 is provided in one of mesa regions of the n−-type drift region 101 divided by the gate trenches 102. An n+-type emitter region 106 is selectively provided, in the front surface layer on the substrate front surface side, in an inner portion of the p-type base region 105. An emitter electrode 107 is in contact with the p-type base region 105 and n+-type emitter region 106 via a contact hole of an interlayer insulating film 108 provided in the substrate front surface, and is electrically insulated from the gate electrode 104 by the interlayer insulating film 108. A p+-type region (hereafter referred to as a floating p+-type region) 109 electrically insulated from the emitter electrode 107 by the interlayer insulating film 108 is provided in a mesa region, in which the n+-type emitter region 106 is not provided, in order to secure a breakdown voltage.
An n-type field stop (FS) layer 110 and a p+-type collector layer 111 are provided on the rear surface side of the n−-type semiconductor substrate. A collector electrode 112 is in contact with the p+-type collector layer 111. In the trench gate IGBT of this kind of heretofore known structure, the potential of the floating p+-type region 109 rises by holes being accumulated in the floating p+-type region 109 when turning on, and a displacement current generated by the rise in potential flows into the gate electrode 104. As the turn-on speed in a period relating to the dV/dt is determined by the inflow of the displacement current, the turn-on dV/dt controllability deteriorates (for example, refer to Non-Patent Literature 1: N. Tokura, Influence of Floating P-Base on Turn-On Characteristics of Trench-Gate FS-IGBT, The Institute of Electrical Engineers of Japan (IEEJ), IEEJ Journal of Industry Applications, Vol. 130, No. 6, pp. 728-733, 2010, and to Non-Patent Literature 2: Y. Onozawa and five others, Development of the next generation 1200V trench-gate FS-IGBT featuring lower EMI noise and lower switching loss, and Proceedings of the 19th International Symposium on Power Semiconductor Devices & ICs, Jeju Island, pp. 13-16, May 27 to 30, 2007)
As a device wherein the trade-off relationship, between the turn-on loss Eon and the dV/dt, and the turn-on dV/dt controllability are improved, the following device is proposed. A first groove and a second groove are formed so as to pass through a p-type base layer and n-type layer and reach the upper layer portion of an n−-type layer. The first groove is adjacent to an N+-type emitter region, and a gate electrode is formed in the inner portion of the first groove. A polysilicon region is formed in the inner portion of the second groove. The second groove is different from the first groove in that no N+-type emitter region is formed in a region in the vicinity of the second groove, and in that no gate electrode is formed in the inner portion of the second groove (for example, refer to JP-A-2002-353456). In JP-A-2002-353456, by forming a dummy gate structure wherein the polysilicon region of emitter potential is provided in the inner portion of the second groove via an insulating film, holes accumulated in the p-type base layer are drawn out to an emitter electrode when in off operation, thus improving off-operation characteristics.
Next, a description will be given of a structure of the active region of the trench gate IGBT including the dummy gate structure. FIG. 25 is a sectional view showing another example of the structure of the heretofore known trench gate IGBT. The trench gate IGBT including the dummy gate structure shown in FIG. 25 includes a trench gate type of MOS gate structure, in the same way as the commonly used trench gate IGBT shown in FIG. 24. Further, a trench (hereafter referred to as an emitter trench) 122 is provided, so as to be adjacent to the trench (gate trench) 102 configuring the MOS gate structure, with the p-type base region 105 between the trench 122 and the adjacent trench 102. An electrode (a dummy gate electrode) 124 of emitter potential is provided in the inner portion of the emitter trench 122 via an insulating film (a dummy gate insulating film) 123.
Components of the trench gate IGBT including the dummy gate structure, other than the emitter trench 122, dummy gate insulating film 123, and dummy gate electrode 124, are the same as those of the commonly used trench gate IGBT shown in FIG. 24. In the trench gate IGBT including the dummy gate structure, holes are accumulated along the emitter trench 122, in particular, when at a high voltage such as when in an early turn-on stage, a low-resistance current path which causes a hole current to flow from the floating p+-type region 109 to the emitter electrode 107 is formed. Therefore, it is possible to suppress a rise in the potential of the floating p+-type region 109, and thus possible to improve the trade-off relationship, between the turn-on loss Eon and the dV/dt, and the turn-on dV/dt controllability using the gate resistance Rg, compared with in the commonly used trench gate IGBT.
However, in the trench gate IGBT including the dummy gate structure, holes are apt to be accumulated in the vicinity of the emitter trench 122, rather than in the vicinity of the gate trench 102, even when at a low voltage such as when in an on-state, thus reducing a resistance relative to the hole current which passes through the p-type base region 105. Therefore, there is the problem that an injection enhancement (IE) effect decreases, thus promoting an increase in the on-voltage. Also, as it is not possible to carry out the screening of the dummy gate insulating film 123 provided along the inner wall of the emitter trench 122, there is the problem that it is difficult to detect a defect of the dummy gate insulating film 123 using a test for detecting a device including an initial detect.
As a device wherein the trade-off relationship, between the turn-on loss Eon and the dV/dt, and the turn-on dV/dt controllability using the gate resistance Rg are improved without providing an emitter trench, a device wherein a second source region is not connected directly to an emitter electrode, due to which a channel for causing charge carriers to flow from the emitter electrode to a drift layer through the second source region and a second base layer is not formed in the second base layer, is proposed (for example, refer to JP-T-2013-522924).
Also, as another device, the following device is proposed. A pair of main trenches are formed so as to pass through a p-type base layer and reach an n-type base layer. A pair of n-type emitter layers are formed, on the front surface of the p-type base layer, in a current path region sandwiched between the main trenches. A narrowed trench is formed between the pair of n-type emitter layers so as to pass through the p-type base layer and reach the n-type base layer. The narrowed trench is such that hole discharge resistance is increased by narrowing a hole discharge path formed from the n-type base layer to the emitter electrode through the p-type base layer (for example, refer to JP-A-2001-168333).
Also, as another device, the following device is proposed. A sub-well region is provided in one portion of a region of an emitter side surface sandwiched between trench gates, and the sub-well region is connected to an emitter electrode via a diode. The diode is placed in a non-continuity state when an IGBT is in an on-state, and the sub-well region is insulated from the emitter electrode, thereby accumulating carriers. The diode is placed in a continuity state when the IGBT is in an off-state, and the sub-well region is electrically connected to the emitter electrode, thereby discharging carriers at a high speed. In an early turn-on stage, the capacity of a gate portion facing the sub-well region is set to a gate-emitter capacity, thereby reducing a gate-collector capacity and reducing the electromagnetic noise when switching (for example, refer to JP-A-2004-335719).
However, when the emitter trench 122 is not provided, the structure positively using the low-resistance current path which causes the holes accumulated in the floating p+-type region 109 to flow to the emitter electrode 107 when turning on is not formed. Therefore, the IE effect is apt to be impaired to the same degree as or more than in the trench gate IGBT including the dummy gate structure, and it is difficult to strike a balance between a reduction in the on-voltage and an improvement in the trade-off relationship between the turn-on loss Eon and the dV/dt.
In order to solve the heretofore described problems due to the heretofore known technologies, the invention has for its object to provide a semiconductor device wherein it is possible to reduce an on-voltage and improve the trade-off relationship, between turn-on loss Eon and dV/dt, and turn-on dV/dt controllability using a gate resistance Rg.